1. Field of the Invention
The present invention relates to semiconductor wafer arrays in general and in particular to a method and apparatus comprising a stacked array of semiconductor wafers which are vertically interconnected by means of a plurality of wads of an electrically conductive compliant material.
2. Description of the Prior Art
Since the development of integrated circuit technology, computers and computer storage devices have been made from wafers of semiconductor material comprising a plurality of integrated transistor circuits. After the wafer is made, the circuits are separated from each other by cutting the wafer into small chips. Thereafter, the chips are bonded to carriers of varying types, interconnected by tiny wires and packaged.
The above-described process of making computers and computer memory devices has been found to be time-consuming and costly and the use of tiny wires to electrically connect the chips has often been found to be unreliable. Moreover, the length of the wires which has been required to make the necessary interconnections between chips has been found to result in undesirable signal delays as the frequency of operation of the devices has increased.
To avoid some of the disadvantages of the prior technology, a number of efforts have been made to eliminate the need for separating chips in a wafer and interconnecting them using wires. For example, a technology called Wafer Scale Integration (WSI) attempted to do this. In WSI, techniques were used to wire together all the chips on a single wafer; however, the attempts thus far have not been successful. It was found that the line widths required to provide a computer on a single wafer, even when multiple layers of lateral connections were used, became so small that it was not possible to obtain lines of sufficient length and precision to make the necessary interconnections between the circuits therein.
The use of WSI technology which uses lateral connections to connect the circuits on a single wafer also has disadvantages when used for making storage devices. In practice, all wafers comprise randomly located defects. The defects render the circuits affected unusable. Since WSI technology incorporates the defective circuits at the time a wafer is made, it is difficult and costly to build in an amount of redundancy sufficient to overcome the effect of the defects. In any event, even if a single wafer comprising a large number of storage cells could be built at a reasonable cost, the memory capacity required in many applications far exceeds that which can be provided on a single wafer. Therefore, such applications would still require that a plurality of such wafers be used and that the wafers be interconnected in some suitable manner.
Other attempts to avoid the disadvantages of interconnecting a plurality of stacked wafers using wires have involved large scale parallel array processors and memory devices in which parallel circuit members are interconnected using vertical columns of solid, dense conductive material such as solder, copper, etc. For example, in U.S. Pat. No. 4,368,106, there is disclosed a process for making a solid, dense metallic feedthrough in a semiconductive material comprising the use of an electroforming solution and apparatus. In U.S. Pat. No. 4,394,712, there is disclosed a process for making a feedthrough in a semiconductor wafer array comprising three solid concentric materials including a central core of solder. In making the array, a plurality of the wafers are stacked and solder, which has been implanted in vias in the wafers and slightly beyond, is caused to flow, interconnecting the wafers.
The use of solid, dense feedthroughs to interconnect a plurality of wafers is typically costly and time consuming and makes it difficult to separate the wafers in the event that a wafer is or becomes defective and requires repair or replacement. The reason for this is that the heat required to form and/or sever the interconnections can be damaging to the wafers and the circuits located therein. Also, differential thermal coefficients of expansion between the rigid feedthroughs and the surrounding semiconductor and other materials can result in damaging stresses during thermal cycling.
In applicant's above-described co-pending patent application there is disclosed a semiconductor wafer array. In the array each wafer is provided with one or more vias, as by chemical or laser drilling or the like. After the walls of the vias and the wafers are coated with a layer of electrically insulating material, the wafers are stacked one on top of another with the vias in one wafer placed in registration with corresponding vias in adjacent wafers and clamped or bonded together as by an adhesive. After the wafers are bonded to a larger diameter interconnection wafer, all of the vias in the array are filled with an electrically conductive liquid. After the vias are filled, the exposed ends of the vias are sealed with compliant material. The array is then packaged with electrical connections made thereto by means of wires connecting pads on the interconnection wafer and externally projecting pin members.
While avoiding the disadvantages associated with rigid vertical electrical feedthroughs, the use of electrically conductive liquid to form the interconnections does require special tooling to fill the vias.
In applications requiring fewer vertical feedthroughs which thus lessen the need for very small vias and the use of an electrically conductive liquid to form the vertical electrical connections, it is found that vias which are somewhat larger may be filled with an electrically conductive compliant material. Such material may, for example, comprise wads of very fine wire or wads of electrically conductive elastomeric material.
The idea of using compliant wadded fine wire, sometimes called "fuzz wire", to make an electrical connection between two electrical conductors is old, dating back to the use of "fuzz wire" to make RF seals in microwave cabinets and waveguides. The idea of using compliant "fuzz wire" for providing vertical connections between individual boards in a stack of printed circuit boards is also known and was proposed in U.S. Pat. Nos. 4,574,331 and 4,581,679 by Robert Smolley.
In his patents Smolley discloses a stack of printed circuit boards. On each of the boards there is provided an electrical contact area or pad. The pad may be formed on the surface of the boards or on a metallic feedthrough inserted in a via in the boards. Interposed between each of the boards there is an insulated board referred to as a button board. The button board has a plurality of circular openings formed through it, and in each opening is placed a connector element, also known as a "fuzz button" or button connector. The button connector is formed from a single strand of metal wire, each strand being wadded together to form a nearly cylindrical "button" of material. When the button elements are placed in the holes, the button material projects slightly out of the holes on both ends. When a compressive force is applied to the stack of printed circuit boards, the insulated board interposed therebetween and the button elements, the latter are compressed against the contact areas or pads forming an electrical connection therebetween.
For several reasons, the use of "fuzz wire" in the manner disclosed by Smolley to form vertical electrical connections between a stack of printed circuit boards has certain disadvantages. For example, to provide vertical electrical connections between a stack of printed circuit boards, metallic feedthroughs are required to be inserted in vias provided in the boards and an insulated board is required to insulate the printed circuit boards from each other and to hold the button elements in place. Because of the cylindrical shape of the button elements, both the metallic feed throughs and the insulated boards are required to make an electrical connection to circuits on the boards and to insure the application of uniform compressive forces to the button elements. These features, the insulated boards and the metalic feedthroughs, require a considerable amount of space and increase the complexity of the manufacturing and assembly process.
In U.S. Pat. No. 4,029,375 issued to Henry Gabrielian, there is disclosed in two embodiments of an electrical connector the use of a cylindrically shaped metalic helical spring member for vertically electrically interconnecting electrical pads located on two spaced-apart printed circuit boards. As in the case of the Smolley invention, however, Gabrielian also requires an intermediate insulating board to both insulate the printed circuit boards from each other and to hold the spring members in position in order to make the necessary electrical connections. The use of an intermediate insulating board to insulate the printed circuit boards from each other and to hold the electrically connecting spring members adds expense to the apparatus, increases the overall size of the apparatus, as well as adding steps to the fabrication of an array using them.